An analytical threshold voltage model for dual-strained channel PMOSFET

doi:10.1088/1674-1056/19/11/117309

Abstract Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si_1-xGe_x/relaxd Si_1-yGe_y(s-Si/s-SiGe/Si_1-yGe_y) metal–oxide–semiconductor field-effect transistor (PMOSFET), analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si), because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si_1-yGe_y metal-oxide-semiconductor field-effect transistor (MOSFET) designs.

Keywords: strained Si strained SiGe dual-channel metal–oxide–semiconductor field-effect transistor (MOSFET) threshold voltage

Received: 16 December 2009
Revised: 22 July 2010
Accepted manuscript online:

PACS:	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.Tv	(Field effect devices)

Fund: Project supported by the National Defence Pre-research Foundation of China (Grant Nos. 51308040203, 9140A08060407DZ0103, and 6139801).

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Qin Shan-Shan(秦珊珊), Zhang He-Ming(张鹤鸣), Hu Hui-Yong(胡辉勇), Dai Xian-Ying(戴显英), Xuan Rong-Xi(宣荣喜), and Shu Bin(舒斌) An analytical threshold voltage model for dual-strained channel PMOSFET 2010 Chin. Phys. B 19 117309

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