Negative gate bias stress effects on conduction and low frequency noise characteristics in p-type poly-Si thin-film transistors

doi:10.1088/1674-1056/28/8/088502

Abstract The instability of p-channel low-temperature polycrystalline silicon thin film transistors (poly-Si TFTs) is investigated under negative gate bias stress (NBS) in this work. Firstly, a series of negative bias stress experiments is performed, the significant degradation behaviors in current-voltage characteristics are observed. As the stress voltage decreases from -25 V to -37 V, the threshold voltage and the sub-threshold swing each show a continuous shift, which is induced by gate oxide trapped charges or interface state. Furthermore, low frequency noise (LFN) values in poly-Si TFTs are measured before and after negative bias stress. The flat-band voltage spectral density is extracted, and the trap concentration located near the Si/SiO₂ interface is also calculated. Finally, the degradation mechanism is discussed based on the current-voltage and LFN results in poly-Si TFTs under NBS, finding out that Si-OH bonds may be broken and form Si^* and negative charge OH^- under negative bias stress, which is demonstrated by the proposed negative charge generation model.

Keywords: polycrystalline silicon thin film transistor negative bias stress low frequency noise

Received: 24 January 2019
Revised: 17 May 2019
Accepted manuscript online:

PACS:	85.30.Tv	(Field effect devices)
	73.40.Qv	(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
	85.40.Qx	(Microcircuit quality, noise, performance, and failure analysis)

Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61574048), the Pearl River Science and Technology Nova Program of Guangzhou City, China (Grant No. 201710010172), the International Science and Technology Cooperation Program of Guangzhou City (Grant No. 201807010006), the International Cooperation Program of Guangdong Province, China (Grant No. 2018A050506044), and the Opening Fund of Key Laboratory of Silicon Device Technology, China (Grant No. KLSDTJJ2018-6).

Corresponding Authors: Yuan Liu
E-mail: eeliuyuan@gdut.edu.cn

Cite this article:

Chao-Yang Han(韩朝阳), Yuan Liu(刘远), Yu-Rong Liu(刘玉荣), Ya-Yi Chen(陈雅怡), Li Wang(王黎), Rong-Sheng Chen(陈荣盛) Negative gate bias stress effects on conduction and low frequency noise characteristics in p-type poly-Si thin-film transistors 2019 Chin. Phys. B 28 088502

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Negative gate bias stress effects on conduction and low frequency noise characteristics in p-type poly-Si thin-film transistors

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