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Chin. Phys. B, 2014, Vol. 23(6): 067101    DOI: 10.1088/1674-1056/23/6/067101
CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES Prev   Next  

Partial-SOI high voltage laterally double-diffused MOS with a partially buried n+-layer

Hu Sheng-Dong (胡盛东)a b, Wu Xing-He (武星河)a, Zhu Zhi (朱志)a, Jin Jing-Jing (金晶晶)a, Chen Yin-Hui (陈银晖)a
a College of Communication Engineering, Chongqing University, Chongqing 400044, China;
b National Laboratory of Analogue Integrated Circuits, No. 24 Research Institute of China Electrics Technology Group Corporation, Chongqing 400044, China
Abstract  A novel partial silicon-on-insulator laterally double-diffused metal-oxide-semiconductor transistor (PSOI LDMOS) with a thin buried oxide layer is proposed in this paper. The key structure feature of the device is an n+-layer, which is partially buried on the bottom interface of the top silicon layer (PBNL PSOI LDMOS). The undepleted interface n+-layer leads to plenty of positive charges accumulated on the interface, which will modulate the distributions of the lateral and vertical electric fields for the device, resulting in a high breakdown voltage (BV). With the same thickness values of the top silicon layer (10 μm) and buried oxide layer (0.375 μm), the BV of the PBNL PSOI LDMOS increases to 432 V from 285 V of the conventional PSOI LDMOS, which is improved by 51.6%.
Keywords:  silicon-on-insulator      breakdown voltage      interface charges      electric field  
Received:  12 October 2013      Revised:  11 December 2013      Accepted manuscript online: 
PACS:  71.10.-w (Theories and models of many-electron systems)  
  73.20.-r (Electron states at surfaces and interfaces)  
  73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))  
  73.40.Ty (Semiconductor-insulator-semiconductor structures)  
Fund: Project supported by the Natural Science Foundation of Chongqing Science and Technology Commission (CQ CSTC) (Grant No. cstcjjA40008), the Fundamental Research Funds for the Central Universities, China (Grant No. CDJZR12160003), the China Postdoctoral Science Foundation (Grant Nos. 2012M511906 and 2013T60835), and Chongqing University Postgraduates' Science and Innovation Fund, China (Grant No. CDJXS12161105).
Corresponding Authors:  Hu Sheng-Dong     E-mail:  hushengdong@hotmail.com

Cite this article: 

Hu Sheng-Dong (胡盛东), Wu Xing-He (武星河), Zhu Zhi (朱志), Jin Jing-Jing (金晶晶), Chen Yin-Hui (陈银晖) Partial-SOI high voltage laterally double-diffused MOS with a partially buried n+-layer 2014 Chin. Phys. B 23 067101

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