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Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs |
| Luo Jie-Xin(罗杰馨)a)b), Chen Jing(陈静)a)†, Zhou Jian-Hua(周建华)a)b), Wu Qing-Qing(伍青青)a)b), Chai Zhan(柴展)a), Yu Tao(余涛)a)c), and Wang Xi(王曦)a) |
a. State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Shanghai 200050, China;
b. Graduate University of Chinese Academy of Sciences, Beijing 100049, China;
c. The Key Laboratory of Thin Films of Jiangsu, Departments of Physics, Soochow University, Suzhou 215006, China |
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Abstract The hysteresis effect in the output characteristics, originating from the floating body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs at different back-gate biases. ID hysteresis has been developed to clarify the hysteresis characteristics. The fabricated devices show the positive and negative peaks in the ID hysteresis. The experimental results show that the ID hysteresis is sensitive to the back gate bias in 0.13-μm PD SOI MOSFETs and does not vary monotonously with the back-gate bias. Based on the steady-state Shockley--Read--Hall (SRH) recombination theory, we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.
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Revised: 27 April 2012
Accepted manuscript online:
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PACS:
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66.70.Df
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(Metals, alloys, and semiconductors)
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68.35.bg
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(Semiconductors)
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73.20.-r
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(Electron states at surfaces and interfaces)
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73.40.Qv
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(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
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| Fund: Project supported by the TCAD Simulation and SPICE Modeling of 0.13μm SOI Technology, China (Grant No. 2009ZX02306-002). |
Cite this article:
Luo Jie-Xin(罗杰馨), Chen Jing(陈静), Zhou Jian-Hua(周建华), Wu Qing-Qing(伍青青), Chai Zhan(柴展), Yu Tao(余涛), and Wang Xi(王曦) Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs 2012 Chin. Phys. B 21 056602
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