An improvement to computational efficiency of the drain current model for double-gate MOSFET

doi:10.1088/1674-1056/20/9/097304

Abstract As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.

Keywords: computational efficiency compact model double-gate MOSFET

Received: 18 January 2011
Revised: 28 February 2011
Accepted manuscript online:

PACS:	73.40.Ty	(Semiconductor-insulator-semiconductor structures)
	73.40.Qv	(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
	61.44.Br	(Quasicrystals)

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Zhou Xing-Ye(周幸叶), Zhang Jian(张健), Zhou Zhi-Ze(周致赜), Zhang Li-Ning(张立宁), Ma Chen-Yue(马晨月), Wu Wen(吴文), Zhao Wei(赵巍), and Zhang Xing(张兴) An improvement to computational efficiency of the drain current model for double-gate MOSFET 2011 Chin. Phys. B 20 097304

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An improvement to computational efficiency of the drain current model for double-gate MOSFET

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