Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures

doi:10.1088/1674-1056/abe2fe

Abstract Trigger characteristics of electrostatic discharge (ESD) protecting devices operating under various ambient temperatures ranging from 30 ℃ to 195 ℃ are investigated. The studied ESD protecting devices are the H-gate NMOS transistors fabricated with a 0.18-μm partially depleted silicon-on-insulator (PDSOI) technology. The measurements are conducted by using a transmission line pulse (TLP) test system. The different temperature-dependent trigger characteristics of grounded-gate (GGNMOS) mode and the gate-triggered (GTNMOS) mode are analyzed in detail. The underlying physical mechanisms related to the effect of temperature on the first breakdown voltage V_T1 are investigated through the assist of technology computer-aided design (TCAD) simulation.

Keywords: ESD trigger voltage temperature GGNMOS GTNMOS TCAD

Received: 09 November 2020
Revised: 04 January 2021
Accepted manuscript online: 04 February 2021

PACS:	85.30.De	(Semiconductor-device characterization, design, and modeling)
	41.20.Cv	(Electrostatics; Poisson and Laplace equations, boundary-value problems)
	85.30.Mn	(Junction breakdown and tunneling devices (including resonance tunneling devices))

Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61804168).

Corresponding Authors: Xiao-Jing Li, Fa-Zhan Zhao
E-mail: lixiaojing1@ime.ac.cn;zhaofazhan@ime.ac.cn

Cite this article:

Jia-Xin Wang(王加鑫), Xiao-Jing Li(李晓静), Fa-Zhan Zhao(赵发展), Chuan-Bin Zeng(曾传滨), Duo-Li Li(李多力), Lin-Chun Gao(高林春), Jiang-Jiang Li(李江江), Bo Li(李博), Zheng-Sheng Han(韩郑生), and Jia-Jun Luo(罗家俊) Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures 2021 Chin. Phys. B 30 078501

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Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures

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