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Chin. Phys. B, 2020, Vol. 29(5): 057701    DOI: 10.1088/1674-1056/ab7e94
CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES Prev   Next  

Variable-K double trenches SOI LDMOS with high-concentration P-pillar

Lijuan Wu(吴丽娟), Lin Zhu(朱琳), Xing Chen(陈星)
The Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering, School of Physics&Electronic Science, Changsha University of Science&Technology, Changsha 410114, China
Abstract  A variable-K trenches silicon-on-insulator (SOI) lateral diffused metal-oxide-semiconductor field-effect transistor (MOSFET) with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields. The device features variable-K dielectric double trenches and a P-pillar between the trenches (VK DT-P LDMOS). The low-K dielectric layer on the surface increases electric field of it. Adding a variable-K material introduces a new electric field peak to the drift region, so as to optimize electric field inside the device. Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it. Thereby, breakdown voltage (BV) of the device is increased. The double conductive channels provide two current paths that significantly reduce specific on-resistance (Ron,sp). Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ·cm2. The Ron,sp of VK DT-P LDMOS is reduced by 78.9% compared with the conventional structure.
Keywords:  variable-K (VK)      trench technology      specific on-resistance (Ron,sp)      breakdown voltage (BV)  
Received:  06 November 2019      Revised:  06 March 2020      Published:  05 May 2020
PACS:  77.55.df (For silicon electronics)  
  85.30.De (Semiconductor-device characterization, design, and modeling)  
  51.50.+v (Electrical properties)  
Fund: Project supported by the Scientific Research Fund of Hunan Provincial Education Department, China (Grant No. 19K001).
Corresponding Authors:  Lijuan Wu     E-mail:  1329456829@qq.com

Cite this article: 

Lijuan Wu(吴丽娟), Lin Zhu(朱琳), Xing Chen(陈星) Variable-K double trenches SOI LDMOS with high-concentration P-pillar 2020 Chin. Phys. B 29 057701

[1] Zhang W, Qiao M, Wu L, Ye K, Wang Z, Wang Z, Luo X, Zhang S, Su W, Zhang B and Li Z 2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD), May 26-30, 2013, Kanazawa, Japan, 329
[2] Qiao M, Jiang L, Wang M. Huang Y, Liao H, Liang T, Sun Z, Zhang B, Li Z, Huang G, Zhao Y, Lai L, Hu X, Zhuang X, Luo X and Wang Z 2011 IEEE 23rd ISPSD, May 23-26, 2011, San Diego, USA, 180
[3] Li Q, Wen Y, Zhang F, Li H, Xiao G, Chen Y and Fu T 2018 Results Phys. 10 46
[4] Xia C, Cheng X H, Wang Z J, Xu D W, Cao D, Zheng L, Shen L Y, Yu Y H and Shen D S 2014 IEEE Trans. Electron. Dev. 61 3477
[5] Ge W, Luo X, Wu J, Lv M, Wei J, Ma D, Deng G, Cui W, Yang Y and Zhu K 2017 IEEE Electron Dev. Lett. 38 910
[6] Zhang J, Guo Y F, Pan D Z, Yang K M, Lian X J and Yao J F 2018 IEEE Trans. Electron Dev. 65 648
[7] Lei J, Hu S, Wang S and Lin Z 2017 Proc. Int. Conf. Electron. Devices Solid-State Circuits (EDSSC), October 18-20, 2017, Hsinchu, Taiwan China, 12
[8] Luo X R, Lei T F, Wang Y G, Yao G L, Jiang Y H, Zhou K, Wang P, Zhang Z Y, Fan J, Wang Q, Ge R, Zhang B, Li Z and Udrea F 2012 IEEE Trans. Electron Dev. 59 504
[9] Luo X R, Fan J, Wang Y G, Lei T F, Qiao M, Zhang B and Udrea F 2011 IEEE Electron Dev. Lett. 32 185
[10] Zhou K. Luo X, Xu Q. Lv M, Zhang B and Li Z 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD), June 15-19, 2014, Waikoloa, USA, 189
[11] Wu L J, Zhang W T, Shi Q, Cai P F and He H C 2014 Electron. Lett. 50 1982
[12] Li H and Chen X 2015 IEEE 11th International Conference on ASIC (ASICON), November 3-6, 2015, Chengdu, China, p. 1
[13] Luo X R, Udrea F, Wang Y G, Yao G L and Liu Y 2010 IEEE Electron Dev. Lett. 31 594
[14] Luo X R, Wang Y G, Deng H, Fan J, Lei T F and Liu Y 2010 IEEE Trans. Electron Dev. 57 535
[15] Hu X R, Zhang B, Luo X R, Jiang Y H and Li Z J 2012 Electron Lett. 48 1235
[16] Hu C M 1979 IEEE Trans. Electron Dev. 26 243
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