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Chin. Phys. B, 2011, Vol. 20(9): 097304    DOI: 10.1088/1674-1056/20/9/097304

An improvement to computational efficiency of the drain current model for double-gate MOSFET

Wu Wena, Zhao Weia, Zhou Xing-Yeb, Zhang Jianb, Zhou Zhi-Zeb, Zhang Li-Ningb, Ma Chen-Yueb, Zhang Xingb
a Peking University Shenzhen SOC Key Laboratory, PKU-HKUST Shenzhen Institution, Shenzhen 518057, China; b TSRC, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871, China
Abstract  As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.
Keywords:  MOSFET      computational efficiency      compact model      double-gate     
Received:  18 January 2011      Published:  15 September 2011
PACS:  73.40.Ty (Semiconductor-insulator-semiconductor structures)  
  73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))  
  61.44.Br (Quasicrystals)  

Cite this article: 

Zhou Xing-Ye, Zhang Jian, Zhou Zhi-Ze, Zhang Li-Ning, Ma Chen-Yue, Wu Wen, Zhao Wei, Zhang Xing An improvement to computational efficiency of the drain current model for double-gate MOSFET 2011 Chin. Phys. B 20 097304

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