中国物理B ›› 2016, Vol. 25 ›› Issue (2): 27306-027306.doi: 10.1088/1674-1056/25/2/027306

• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇    下一篇

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

Yan-Hui Zhang(张彦辉), Jie Wei(魏杰), Chao Yin(尹超), Qiao Tan(谭桥), Jian-Ping Liu(刘建平), Peng-Cheng Li(李鹏程), Xiao-Rong Luo(罗小蓉)   

  1. 1. State Key Laboratory of Electronic Thin Films and Integrated Devices. University of Electronic Science and Technology of China, Chengdu 610054, China;
    2. Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, China
  • 收稿日期:2015-08-10 修回日期:2015-10-12 出版日期:2016-02-05 发布日期:2016-02-05
  • 通讯作者: Xiao-Rong Luo E-mail:xrluo@uestc.edu.cn
  • 基金资助:
    Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079).

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

Yan-Hui Zhang(张彦辉)1, Jie Wei(魏杰)1, Chao Yin(尹超)1, Qiao Tan(谭桥)1, Jian-Ping Liu(刘建平)1, Peng-Cheng Li(李鹏程)1, Xiao-Rong Luo(罗小蓉)1,2   

  1. 1. State Key Laboratory of Electronic Thin Films and Integrated Devices. University of Electronic Science and Technology of China, Chengdu 610054, China;
    2. Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, China
  • Received:2015-08-10 Revised:2015-10-12 Online:2016-02-05 Published:2016-02-05
  • Contact: Xiao-Rong Luo E-mail:xrluo@uestc.edu.cn
  • Supported by:
    Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079).

摘要: A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P- region and two diodes in series. In the on-state with VGD>0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the “hot-spot” caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V.

关键词: LDMOS, accumulation gate, back-side etching, breakdown voltage, specific on-resistance

Abstract: A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P- region and two diodes in series. In the on-state with VGD>0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the “hot-spot” caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V.

Key words: LDMOS, accumulation gate, back-side etching, breakdown voltage, specific on-resistance

中图分类号:  (Semiconductor-insulator-semiconductor structures)

  • 73.40.Ty
85.30.De (Semiconductor-device characterization, design, and modeling) 85.30.Tv (Field effect devices)