A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

doi:10.1088/1674-1056/19/7/077306

中国物理B ›› 2010, Vol. 19 ›› Issue (7): 77306-077306.doi: 10.1088/1674-1056/19/7/077306

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

Florin Udrea¹, 王元刚², 邓浩², 罗小蓉³

(1)Department of Engineering, University of Cambridge, Cambridge, CB3 0FA, UK; (2)State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China; (3)State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;Department of Engineering, University of Cambridge, Cambridge, CB3 0FA, UK

修回日期:2010-02-01 出版日期:2010-07-15 发布日期:2010-07-15
基金资助:
Projects supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060), the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904), and the Youth Teacher Foundation of the University of Electronic Science and Technology of China (Grant No. jx0721).

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

Luo Xiao-Rong (罗小蓉)^ab, Wang Yuan-Gang (王元刚)^a, Deng Hao (邓浩)^a, Florin Udrea^b

^a State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China; ^b Department of Engineering, University of Cambridge, Cambridge, CB3 0FA, UK

Revised:2010-02-01 Online:2010-07-15 Published:2010-07-15
Supported by:
Projects supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060), the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904), and the Youth Teacher Foundation of the University of Electronic Science and Technology of China (Grant No. jx0721).

摘要/Abstract

摘要： A novel partial silicon-on-insulator (PSOI) high voltage device with a low-k (relative permittivity) dielectric buried layer (LK PSOI) and its breakdown mechanism are presented and investigated by MEDICI. At a low k value the electric field strength in the dielectric buried layer (E_I) is enhanced and a Si window makes the substrate share the vertical drop, resulting in a high vertical breakdown voltage; in the lateral direction, a high electric field peak is introduced at the Si window, which modulates the electric field distribution in the SOI layer; consequently, a high breakdown voltage (BV) is obtained. The values of E_I and BV of LK PSOI with k_I=2 on a 2 μm thick SOI layer over 1 μm thick buried layer are enhanced by 74% and 19%, respectively, compared with those of the conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect.

Abstract: A novel partial silicon-on-insulator (PSOI) high voltage device with a low-k (relative permittivity) dielectric buried layer (LK PSOI) and its breakdown mechanism are presented and investigated by MEDICI. At a low k value the electric field strength in the dielectric buried layer (E_I) is enhanced and a Si window makes the substrate share the vertical drop, resulting in a high vertical breakdown voltage; in the lateral direction, a high electric field peak is introduced at the Si window, which modulates the electric field distribution in the SOI layer; consequently, a high breakdown voltage (BV) is obtained. The values of E_I and BV of LK PSOI with k_I= 2 on a 2 μm thick SOI layer over 1 μm thick buried layer are enhanced by 74% and 19%, respectively, compared with those of the conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect.

Key words: silicon-on-insulator, low k dielectric, electric field, breakdown voltage

中图分类号: (Field effect devices)

85.30.Tv

85.50.-n (Dielectric, ferroelectric, and piezoelectric devices) 77.22.Ch (Permittivity (dielectric function)) 77.22.Jp (Dielectric breakdown and space-charge effects)

罗小蓉, 王元刚, 邓浩, Florin Udrea. A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer[J]. 中国物理B, 2010, 19(7): 77306-077306.

Luo Xiao-Rong (罗小蓉), Wang Yuan-Gang (王元刚), Deng Hao (邓浩), Florin Udrea. A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer[J]. Chin. Phys. B, 2010, 19(7): 77306-077306.

参考文献 22

[1]	Nakagawa A, Yasuhara N and Baba Y 1991 IEEE Trans. Electron Devices bf38 1650
[2]	Merchant S, Arnold E and Baumgart H 1991 Proc. IEEE Int. Symp. Power Semiconductor Devices and IC's (Bal-timore, MD, USA) p31
[3]	Luo X R, Zhang B and Li Z J 2007 IEEE Electron Device Letters bf28 422
[4]	Luo X R, Zhang B and Li Z J 2008 IEEE Electron Devices Letters bf29 1395
[5]	Luo X R, Zhang B and Li Z J 2008 IEEE Trans. Electron Devices bf55 1756
[6]	Luo X R, Lei T F, Wang Y G, Gao H M and Zhang W 2009 IEEE Electron Device Letters bf30 1093
[7]	Funaki H, Yamaguchi Y and Hirayama K 1998 Proc.10th Int. Symp. Power Semiconductor Devices and IC's (Tokyo, Japan) p25
[8]	Kapels H, Plikat R and Silber D 2000 Proc.10th Int. Symp. Power Semiconductor Devices and IC's (Toulouse. France) p205
[9]	Hu S D, Li Z J and Zhang B 2009 Chin. Phys. B bf18 315
[10]	Hu S D, Li Z J, Zhang B and Luo X R 2010 Chin. Phys. B bf19 037303
[11]	Luo X R, Zhang B and Li Z J 2007 Solid-State Electron. bf51 493
[12]	Delan A, Rennau M, Schulz S E and Gessner T 2003 Microelectronic Engineering bf70 280
[13]	Udrea F, Milne W and Popescu A1997 Electron. Lett. bf33 907
[14]	Tadikonda R, Hardikar S and Sankara N E M 2004 Solid-State Electron. bf48 1655
[15]	Guo Y F, Fang J, Zhang B and Li Z J 2005 Chinese Journal of Semiconductors bf26 33
[16]	Hoofman R J O M, Verheijden G J A M, Michelon J, Iacopi F and Travaly Y 2005 Microelectronic Engineering bf80 337
[17]	Lee S and Park J W 1999 Journal Vacuum Science Technology A bf7 458
[18]	Wang P F, Ding S J, Zhang W, Wang J T and Li W 2001 Microfabrication Technology bf1 30
[19]	Shamiryan D, Abell T, F Iacopi and Maex K 2004 Materials Today bf7 34
[20]	Lubguban J Seitob A Kurata Y, Inokuma T and Hasegawa S 1999 Thin Solid Films bf337 67
[21]	Yun S M, Chang H Y, Kang M S and Choi C K 1999 Thin Solid Films bf341 109
[22]	Bradbury D R, Piedmont C W T and Kamins T I 1985 US Patent No. 4522662

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

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