Design of a novel high holding voltage LVTSCR with embedded clamping diode

doi:10.1088/1674-1056/ab836e

中国物理B ›› 2020, Vol. 29 ›› Issue (6): 68503-068503.doi: 10.1088/1674-1056/ab836e

• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇下一篇

Design of a novel high holding voltage LVTSCR with embedded clamping diode

Ling Zhu(朱玲), Hai-Lian Liang(梁海莲), Xiao-Feng Gu(顾晓峰), Jie Xu(许杰)

Engineering Research Center of IoT Technology Applications(Ministry of Education), Department of Electronic Engineering, Jiangnan University, Wuxi 214122, China

收稿日期:2019-12-04 修回日期:2020-03-18 出版日期:2020-06-05 发布日期:2020-06-05
通讯作者: Xiao-Feng Gu E-mail:xgu@jiangnan.edu.cn
基金资助:
Project supported by the National Natural Science Foundation of China (Grant No. 61504049) and the China Postdoctoral Science Foundation (Grant No. 2016M600361).

Design of a novel high holding voltage LVTSCR with embedded clamping diode

Ling Zhu(朱玲), Hai-Lian Liang(梁海莲), Xiao-Feng Gu(顾晓峰), Jie Xu(许杰)

Engineering Research Center of IoT Technology Applications(Ministry of Education), Department of Electronic Engineering, Jiangnan University, Wuxi 214122, China

Received:2019-12-04 Revised:2020-03-18 Online:2020-06-05 Published:2020-06-05
Contact: Xiao-Feng Gu E-mail:xgu@jiangnan.edu.cn
Supported by:
Project supported by the National Natural Science Foundation of China (Grant No. 61504049) and the China Postdoctoral Science Foundation (Grant No. 2016M600361).

摘要/Abstract

摘要： In order to reduce the latch-up risk of the traditional low-voltage-triggered silicon controlled rectifier (LVTSCR), a novel LVTSCR with embedded clamping diode (DC-LVTSCR) is proposed and verified in a 0.18-μm CMOS process. By embedding a p⁺ implant region into the drain of NMOS in the traditional LVTSCR, a reversed Zener diode is formed by the p⁺ implant region and the n⁺ bridge, which helps to improve the holding voltage and decrease the snapback region. The physical mechanisms of the LVTSCR and DC-LVTSCR are investigated in detail by transmission line pulse (TLP) tests and TCAD simulations. The TLP test results show that, compared with the traditional LVTSCR, the DC-LVTSCR exhibits a higher holding voltage of 6.2 V due to the embedded clamping diode. By further optimizing a key parameter of the DC-LVTSCR, the holding voltage can be effectively increased to 8.7 V. Therefore, the DC-LVTSCR is a promising ESD protection device for circuits with the operation voltage of 5.5-7 V.

关键词: electrostatic discharge, silicon controlled rectifier, clamping diode, holding voltage

Abstract: In order to reduce the latch-up risk of the traditional low-voltage-triggered silicon controlled rectifier (LVTSCR), a novel LVTSCR with embedded clamping diode (DC-LVTSCR) is proposed and verified in a 0.18-μm CMOS process. By embedding a p⁺ implant region into the drain of NMOS in the traditional LVTSCR, a reversed Zener diode is formed by the p⁺ implant region and the n⁺ bridge, which helps to improve the holding voltage and decrease the snapback region. The physical mechanisms of the LVTSCR and DC-LVTSCR are investigated in detail by transmission line pulse (TLP) tests and TCAD simulations. The TLP test results show that, compared with the traditional LVTSCR, the DC-LVTSCR exhibits a higher holding voltage of 6.2 V due to the embedded clamping diode. By further optimizing a key parameter of the DC-LVTSCR, the holding voltage can be effectively increased to 8.7 V. Therefore, the DC-LVTSCR is a promising ESD protection device for circuits with the operation voltage of 5.5-7 V.

Key words: electrostatic discharge, silicon controlled rectifier, clamping diode, holding voltage

中图分类号: (Semiconductor-device characterization, design, and modeling)

85.30.De

85.30.Mn (Junction breakdown and tunneling devices (including resonance tunneling devices)) 73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))

朱玲, 梁海莲, 顾晓峰, 许杰. Design of a novel high holding voltage LVTSCR with embedded clamping diode[J]. 中国物理B, 2020, 29(6): 68503-068503.

Ling Zhu(朱玲), Hai-Lian Liang(梁海莲), Xiao-Feng Gu(顾晓峰), Jie Xu(许杰). Design of a novel high holding voltage LVTSCR with embedded clamping diode[J]. Chin. Phys. B, 2020, 29(6): 68503-068503.

参考文献 16

[1]	Ker M D and Hsu K C 2005 IEEE Trans. Device Mater. Reliab. 5 235 doi: 10.1109/TDMR.2005.846824
[2]	Blaho M, Zullino L, Wolf H, Stella R, Andreini A, Gieser H A, Pogany D and Gornik E 2004 IEEE Trans. Device Mater. Reliab. 4 535 doi: 10.1109/TDMR.2004.836164
[3]	Song B, Han Y, Li M, Dong S, Guo W, Huang D, Ma F and Miao M 2010 Electron. Lett. 46 518 doi: 10.1049/el.2010.0205
[4]	Du F B, Song S Y, Hou F, Song W Q, Chen L, Liu J Z, Liu Z W and Liou J J 2019 IEEE Electron Device Lett. 40 1491 doi: 10.1109/LED.2019.2926103
[5]	Guan J, Wang Y, Hao S W, Zheng Y F and Jin X L 2017 IEEE Electron Device Lett. 38 1716 doi: 10.1109/LED.2017.2766686
[6]	Qi Z, Qiao M, He Y T and Zhang B 2017 Chin. Phys. B 26 077304 doi: 10.1088/1674-1056/26/7/077304
[7]	Xie H L, Feng H G, Zhan R Y, Wang A, Rodriguez D and Rice D 2005 IEEE Electron Device Lett. 26 121 doi: 10.1109/LED.2004.841860
[8]	Lin C Y, Wu Y H and Ker M D 2016 IEEE Electron Device Lett. 37 1387 doi: 10.1109/LED.2016.2608721
[9]	Lou L F and Liou J J 2007 IEEE Electron Device Lett. 28 1120 doi: 10.1109/LED.2007.909838
[10]	Chatterjee A and Polgreen T 1991 IEEE Electron Device Lett. 12 21 doi: 10.1109/55.75685
[11]	Zhang S, Dong S R, Wu X J, Zeng J, Zhong L and Wu J 2015 Chin. Phys. B 24 108502 doi: 10.1088/1674-1056/24/10/108502
[12]	Liu J Z, Qian L L, Tian R, Liu Z W, Zhao L and Cheng H 2017 Microelectron. Reliab. 71 1
[13]	Huang X Z, Liou J J, Liu Z W, Liu F, Liu J Z and Cheng H 2016 IEEE Electron Device Lett. 37 1311 doi: 10.1109/LED.2016.2598063
[14]	Qi Z, Qiao M, Liang L F, Zhang F B, Zhou X, Cheng S K, Zhang S, Lin F, Sun G P, Li Z J and Zhang B 2019 IEEE Electron Device Lett. 40 435 doi: 10.1109/LED.2019.2894646
[15]	Dong S R, Miao M, Wu J, Zeng J, Liu Z W and Liou J J 2013 IEEE Trans. Electromagn. Compat. 55 241 doi: 10.1109/TEMC.2012.2216271
[16]	Liang H L, Xu Q, Zhu L, Gu X F, Sun G P, Lin F, Zhang S, Xiao K and Yu Z G 2019 IEEE Electron Device Lett. 40 163 doi: 10.1109/LED.2018.2890105

Design of a novel high holding voltage LVTSCR with embedded clamping diode

Design of a novel high holding voltage LVTSCR with embedded clamping diode

RichHTML

PDF (PC)

赞

可视化

摘要/Abstract

引用本文

使用本文

参考文献 16

相关文章 11

Metrics

本文评价

推荐阅读 0

[1]	Tian-Tian Xie(谢田田), Jun Wang(王俊), Fei-Bo Du(杜飞波), Yang Yu(郁扬), Yan-Fei Cai(蔡燕飞), Er-Yuan Feng(冯二媛), Fei Hou(侯飞), and Zhi-Wei Liu(刘志伟). Dynamic electrostatic-discharge path investigation relied on different impact energies in metal-oxide-semiconductor circuits[J]. 中国物理B, 2023, 32(4): 48501-048501.
[2]	Yuankang Chen(陈远康), Yuanliang Zhou(周远良), Jie Jiang(蒋杰), Tingke Rao(饶庭柯), Wugang Liao(廖武刚), and Junjie Liu(刘俊杰). Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection[J]. 中国物理B, 2023, 32(2): 28502-028502.
[3]	Xi-Kun Feng(冯希昆), Xiao-Feng Gu(顾晓峰), Qin-Ling Ma(马琴玲), Yan-Ni Yang(杨燕妮), and Hai-Lian Liang(梁海莲). Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN[J]. 中国物理B, 2021, 30(7): 78502-078502.
[4]	Jie Xu(许杰), Nai-Long He(何乃龙), Hai-Lian Liang(梁海莲), Sen Zhang(张森), Yu-De Jiang(姜玉德), and Xiao-Feng Gu(顾晓峰). Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness[J]. 中国物理B, 2021, 30(6): 67303-067303.
[5]	宋文强, 侯飞, 杜飞波, 刘志伟, 刘俊杰. Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications[J]. 中国物理B, 2020, 29(9): 98502-098502.
[6]	齐钊, 乔明, 何逸涛, 张波. High holding voltage SCR for robust electrostatic discharge protection[J]. 中国物理B, 2017, 26(7): 77304-077304.
[7]	张立忠, 王源, 何燕冬. Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress[J]. 中国物理B, 2016, 25(12): 128501-128501.
[8]	马金荣, 乔明, 张波. Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application[J]. , 2015, 24(4): 47303-047303.
[9]	张帅, 董树荣, 吴晓京, 曾杰, 钟雷, 吴健. An improved GGNMOS triggered SCR for high holding voltage ESD protection applications[J]. 中国物理B, 2015, 24(10): 108502-108502.
[10]	张立忠, 王源, 陆光易, 曹健, 张兴. A novel diode string triggered gated-PiN junction device for electrostatic discharge protection in 65-nm CMOS technology[J]. 中国物理B, 2015, 24(10): 108503-108503.
[11]	王　源, 贾　嵩, 陈中建, 吉利久. Low-parasitic ESD protection strategy for RF ICs in 0.35μm CMOS process[J]. 中国物理B, 2006, 15(10): 2297-2305.