Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

doi:10.1088/1674-1056/23/7/078401

›› 2014, Vol. 23 ›› Issue (7): 78401-078401.doi: 10.1088/1674-1056/23/7/078401

• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇下一篇

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

朱思衡^a, 司黎明^a, 郭超^a, 史君宇^a, 朱卫仁^b

a Beijing Key Laboratory of Millimeter Wave and Terahertz Technology, Department of Electronic Engineering, School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;
b Advanced Computing and Simulation Laboratory (AχL), Department of Electrical and Computer Systems Engineering, Monash University, Clayton, Victoria 3800, Australia

收稿日期:2013-10-29 修回日期:2013-12-30 出版日期:2014-07-15 发布日期:2014-07-15
基金资助:
Project supported by the National Natural Science Foundation of China (Grant No. 61307128), the National Basic Research Program of China (Grant No. 2010CB327505), the Specialized Research Found for the Doctoral Program of Higher Education of China (Grant No. 20131101120027), and the Basic Research Foundation of Beijing Institute of Technology of China (Grant No. 20120542015).

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

Zhu Si-Heng (朱思衡)^a, Si Li-Ming (司黎明)^a, Guo Chao (郭超)^a, Shi Jun-Yu (史君宇)^a, Zhu Wei-Ren (朱卫仁)^b

a Beijing Key Laboratory of Millimeter Wave and Terahertz Technology, Department of Electronic Engineering, School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;
b Advanced Computing and Simulation Laboratory (AχL), Department of Electrical and Computer Systems Engineering, Monash University, Clayton, Victoria 3800, Australia

Received:2013-10-29 Revised:2013-12-30 Online:2014-07-15 Published:2014-07-15
Contact: Si Li-Ming E-mail:lms@bit.edu.cn
About author:84.40.Lj; 85.40.-e; 84.40.Dc
Supported by:
Project supported by the National Natural Science Foundation of China (Grant No. 61307128), the National Basic Research Program of China (Grant No. 2010CB327505), the Specialized Research Found for the Doctoral Program of Higher Education of China (Grant No. 20131101120027), and the Basic Research Foundation of Beijing Institute of Technology of China (Grant No. 20120542015).

摘要/Abstract

摘要： We propose a novel hybrid phase-locked loop (PLL) architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator (VCO) and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor (CMOS) process with a total die area of 1.4× 0.46 mm². The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

关键词: phase-locked loop (PLL), fast locking time, low spur, complementary metal oxide semiconductor (CMOS)

Abstract: We propose a novel hybrid phase-locked loop (PLL) architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator (VCO) and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor (CMOS) process with a total die area of 1.4× 0.46 mm². The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

Key words: phase-locked loop (PLL), fast locking time, low spur, complementary metal oxide semiconductor (CMOS)

中图分类号: (Microwave integrated electronics)

84.40.Lj

85.40.-e (Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology) 84.40.Dc (Microwave circuits)

朱思衡, 司黎明, 郭超, 史君宇, 朱卫仁. Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process[J]. , 2014, 23(7): 78401-078401.

Zhu Si-Heng (朱思衡), Si Li-Ming (司黎明), Guo Chao (郭超), Shi Jun-Yu (史君宇), Zhu Wei-Ren (朱卫仁). Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process[J]. Chin. Phys. B, 2014, 23(7): 78401-078401.

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Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

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